Superconducting integrated circuits are roughly classified into two types. One type utilizes strong nonlinearity that appears in the current-voltage characteristic of a Josephson junction and is called a voltage-type logic. The voltage-type logic is the same in logic form as a logic used in semiconductor integrated circuits. The other type utilizes nonlinearity of the current-phase characteristic in a Josephson junction and is called a fluxoid logic.
The voltage-type logic superconducting integrated circuit is a circuit having a feature to output a predetermined voltage (normally, state “0” is set to a zero voltage level and state “1” to a desired output voltage level) for a fixed time (e.g. during a clock period) and carries out logical operation according to the voltage level. An operation signal of the voltage-type logic superconducting integrated circuit is also called a level signal because it takes a constant value during the operation period (clock period) of the circuit. Normally, in the voltage-type logic superconducting integrated circuit, Josephson junctions in an underdamped state with a McCumber coefficient of “50” or more are biased by alternating current so as to be used.
The McCumber coefficient is a constant showing the characteristic of a Josephson junction and is given by “2πI0CRD2/Φ0”, where “I0” represents a critical current value of the Josephson junction, “C” a capacitance, “RD” a resistance value, and “Φ0” a single flux quantum (SFQ) (Non-Patent Document 1: “Ultra-High Speed Josephson Device”, p. 38, published by Baifukan). The Josephson junction with the McCumber coefficient of “50” or more is, once switching to the voltage state, does not return to the superconducting state unless the power supply current (bias current) is set to zero, and hence is used with an AC power supply. In terms of such a characteristic, the voltage-type logic Josephson junction is also sometimes called a latching device.
On the other hand, the fluxoid logic superconducting integrated circuit is a circuit having a feature to output pulses caused by flux quantum and, particularly, a circuit using a single flux quantum (SFQ) as an information carrier is called an SFQ circuit. The SFQ circuit is a circuit that carries out logical operation according to propagation of single flux quantum (SFQ) pulses and the quantum state of the circuit, and its logic is also called a pulse logic because operation signals of the SFQ circuit are in the form of SFQ pulses. Normally, in the SFQ circuit, Josephson junctions in an overdamped state with a McCumber coefficient of approximately “1” are biased by direct current so as to be used. Such an SFQ circuit has a merit that it operates with a DC power supply and is operable at ultra-low power consumption and at ultra-high speed.
The Josephson junction largely changes in operation characteristic according to a value of the McCumber coefficient. The Josephson junction with the McCumber coefficient of approximately “1” used in the SFQ circuit is characterized in that when the Josephson junction switches by an input of one SFQ pulse, it produces one SFQ pulse and automatically returns to the superconducting state. Therefore, it can be operated by the use of the DC power supply. On the other hand, the Josephson junction (latching device) with the McCumber coefficient of “50” or more used in the voltage-type logic circuit is characterized in that it maintains a constant voltage level (this is the state where SFQ pulses are continuously produced) once switching to the voltage state and does not return to the superconducting state unless the power supply current is set to zero. Note that the McCumber coefficient depends on several junction parameters in an actual Josephson junction. Although the McCumber coefficient is as large as approximately several hundreds to several tens of thousands in a Nb/AlOX/Nb junction with a critical current density of approximately 2.5 kA/cm2 to 10 kA/cm2, the Josephson junction with the McCumber coefficient of “1” or that of “50” or more can be easily realized by connecting a resistance of a required value in parallel to the Josephson junction.
A superconducting RAM is, like a semiconductor RAM, formed by decoder circuits, drive circuits, sense circuits, and a memory cell array. The memory cell array is in the form of memory cells arranged in a two-dimensional matrix array shape. In the RAM, information is written into a memory cell designated by an address signal such that two decoder circuits for lateral and vertical directions select a row and a column of the matrix array based on the address signal and, in response thereto, a drive circuit propagates a data signal (information) to the memory cell array. Likewise, a sense circuit reads a data signal (information) stored in a memory cell selected by a signal indicative of a row and a column of the matrix array corresponding to an address.
The conventional superconducting RAM structure has a problem that when the scale (storage capacity) of an RAM increases, a matrix array of memory cells also increases in scale and hence the number of memory cells driven by one drive circuit or sense circuit (the number of memory cells in one row or column) increases, leading to an increase in operating time.
In order to solve this problem, for example, Japanese Unexamined Patent Publication (JP-A) No. 2000-260187 (Patent Document 1) proposes a method of dividing a RAM into small blocks.
This proposal will be described with reference to FIGS. 31 and 32.
FIG. 31 shows one example of a block configuration diagram of a conventional superconducting RAM (random access memory) proposed in Patent Document 1. FIG. 32 shows one example of a 256-RAM block 51.
The superconducting RAM shown in FIG. 31 is one example of a 16 kbit RAM structure formed by 64 256-RAM blocks 51. The illustrated superconducting RAM comprises the 256-RAM blocks 51, block decoder circuits 52, block sense circuits 53, voltage-type logic drive circuits (alternating current bias) 54 that carry out signal propagation between the blocks, impedance matching lines 55 that connect the foregoing respective circuits, and LC resonant circuits 56 that supply high-frequency alternating current (AC).
Each 256-RAM block 51 comprises a 16-row 16-column memory cell array, a voltage-type logic drive circuit 61 and sense circuit 62 each formed by superconducting latching devices biased by alternating current, and a decoder circuit 63 formed by superconducting single flux quantum (SFQ) devices biased by direct current.
In this circuit, in order to enable 10 GHz clock operation, the capacity of the memory cell array driven by the single voltage-type logic drive circuit 61 is limited to 16-row 16-column 256 bits. Therefore, the multidrive system is employed which transfers in parallel signals to many RAM blocks. In this manner, in the conventional superconducting random access memory, the RAM is divided into the small RAM blocks each being the 256-RAM block, thereby limiting the capacity of the memory cell array driven by each drive circuit to enable the high-speed operation. Further, the voltage-type logic drive circuits adapted to operate with an AC power supply and the impedance matching lines are used for the signal propagation between the blocks, thereby enabling the high-speed operation of the RAM as a whole.
In a random access memory, a specific memory cell is selected according to a consistency logic of signals from two directions, i.e. a row direction (lateral) and a column direction (vertical) of a matrix array, and information is written into or read from the selected memory cell. In order to perform this consistency logic in a two-dimensional matrix array of memory cells, it is desirable that the output of a drive circuit for driving the memory cell array be a level-logic signal (rectangular wave signal). It is difficult to achieve the two-direction consistency logic with SFQ pulses having a pulse width of several picoseconds or less.
Accordingly, in a conventional superconducting RAM, a drive circuit formed by voltage logic type (level logic type) latching devices is used (e.g. Patent Document 2: Japanese Unexamined Patent Publication (JP-A) No. H05-191253). However, since the voltage logic type latching device should be operated by an AC power supply, there is a large problem in terms of the power consumption and high-speed operation. In view of this, several proposals have been made for superconducting drive circuits adapted to operate with a DC power supply and, as a typical one among them, there is a circuit as shown in FIG. 33 (Non-Patent Document 2: IBM J. RES. DEVELOP., vol. 24, no. 2, pp. 143-154, March 1980).
In FIG. 33, this circuit comprises a drive gate (G1), a reset gate (G2), superconducting striplines (SL1) and (SL2), damping resistances (Rd1) and (Rd2), and a bias resistance (Rb1). The drive gate (G1) and the damping resistance (Rd1) are connected between a signal output end (D) and a bias current output end (E). The reset gate (G2) and the damping resistance (Rd2) are connected between a connection end (F) and a connection end (G). The superconducting stripline (SL1) is connected between the signal output end (D) and the connection end (F), and the superconducting stripline (SL2) is connected between the bias current output end (E) and the connection end (G). The bias current output end (E) is grounded and supplied with a DC bias current of a predetermined value through the bias resistance (Rb1) connected to a bias current input end (A). The superconducting stripline (SL1), the reset gate (G2), and the superconducting stripline (SL2) constitute a loop circuit that serves as a driven line.
The drive gate (G1) and the reset gate (G2) are gates each having a function of switching to the voltage state when an input signal (rectangular wave signal) of a predetermined value is input, and each formed by a magnetic field coupling quantum interference device having a superconducting loop including two Josephson junctions and a control wire disposed so as to magnetically coupled to the superconducting loop (Non-Patent Document 3: IBM J. RES. DEVELOP., FIG. 2, vol. 24, no. 2, pp. 143-154, March 1980).
FIG. 34 shows operation waveforms of the foregoing conventional superconducting drive circuit. Referring to FIG. 34, the operation of this conventional drive circuit will be described.
In FIG. 34, the axis of ordinates represents a current value, while the axis of abscissas represents a time. The waveform indicated by a thick solid line is an output current (WC) that flows in the superconducting stripline (SL1), while the rectangular waveforms indicated by broken lines are a data signal (WA) and a reset signal (WB).
At first, the bias current supplied through the bias resistance (Rb1) is flowing to ground through the drive gate (G1) in the superconducting state. In this state, when the rectangular-wave data signal (WA) is input into the drive gate (G1), the drive gate (G1) switches to the voltage state and causes the bias current flowing to the drive gate (G1) to be injected into the superconducting stripline (SL1). Therefore, the output current (WC) flowing in the superconducting stripline (SL1) starts to increase and, after the lapse of a fixed time, reaches a predetermined current value. In this event, the drive gate (G1) returns to the superconducting state when the bias current is injected into the superconducting stripline and further the input signal drops to zero, but the constant output current continues to flow in the superconducting stripline. Then, when the rectangular-wave reset signal (WB) is input into the reset gate (G2), the reset gate (G2) switches to the voltage state and hence the output current flowing in the superconducting stripline starts to decrease and reaches zero after the lapse of a fixed time. In this event, the bias current flows through the drive gate (G1), thereby returning to the initial state.
Through the foregoing operation, it is possible to realize the superconducting drive circuit operable with the DC power supply, which can deliver the output current to the superconducting stripline being the driven line when the data signal is input, while, can cause the output current to be zero by the reset signal.
On the other hand, a circuit for reading information “1” or “0” stored in a memory cell selected from a two-dimensional matrix array of memory cells is a sense circuit.
Conventionally, there have been proposed roughly two types of such sense circuits. One is a sense circuit formed by voltage logic type (level logic type) latching devices, which is disclosed, for example, in Japanese Patent Publication No. H03-35757 (Patent Document 3). However, since the voltage logic type latching device should be operated by an AC power supply, there is a large problem in terms of the power consumption and high-speed operation.
The other is a sense circuit adapted to operate with a DC power supply and there is, for example, a sense-bus superconducting sense circuit reported in Non-Patent Document 4 (IBM J. RES. DEVELOP., vol. 24, no. 2, pp. 143-154, March 1980).
Next, the conventional technique will be described with reference to FIGS. 35 and 36.
FIG. 35 is an equivalent circuit diagram of the conventional DC power supply driven superconducting sense circuit. The circuit comprises sense lines (hereinafter referred to as “S lines”) 71-X being part of a memory cell array, gates (GB) 72-X including Josephson junctions and disposed so as to be magnetically coupled to the S lines 71-X, respectively, and a sense bus loop 73 connecting in series the gates (GB) 72-X.
FIG. 36 is a schematic diagram of operation waveforms in this conventional sense-bus superconducting sense circuit. In FIG. 36, the axis of ordinates represents a current value, while the axis of abscissas represents a time. FIG. 36 shows, from top to bottom, a waveform of a current ISB that flows in the sense bus loop 73, a waveform of a current IS that flows in the S line 71-X, a waveform of a current (Ii) that flows in an inductance (Li) of the gate GB 72-X, and a waveform of a current (ID) that flows in a control wire of an output gate (GC) 74.
Based on these operation waveforms, the operation of the conventional circuit will be described.
At first, the operation of this circuit will be briefly explained. When a selected memory cell of the memory cell array holds data “1”, a sense gate of the selected memory cell in the S line 71-X switches to the voltage state by a read operation of the memory cell array, so that the current IS flowing in the S line 71-X drops to zero. This causes the current Ii to temporarily flow in the gate GB 71-X magnetically coupled to the S line 71-X. As a result, the gate GB 72-X switches to the voltage state to drop the current ISB flowing in the sense bus loop 73 to zero. This results in that the current of the sense bus loop 73 flows through the control wire of the output gate GC 74 and a gate GA 75 and hence the output gate GC 74 switches to the voltage state to output information “1”.
As described above, this sense circuit is a circuit adapted to detect the fall of the current IS in the S line (sense line) 71-X. However, although the current IS in the S line 71-X does not drop by a read operation of the memory cell array when information of a memory cell is “0”, it is necessary to drop a waveform of the current IS as indicated by a dotted line in the figure at the end of an operation period (clock). Also in this event, the gate GB 71-X is temporarily set to the voltage state so that the current is input into the control wire of the output gate GC 74. However, in this event, it is necessary that a bias current for the output gate GC 74 be prevented from flowing.
Through the foregoing operation, it is possible to realize the superconducting sense circuit operable with the DC power supply, which can read information of a selected memory cell of the memory cell array.
On the other hand, as a device structure of a conventional superconducting RAM, the device structure is reported which is composed of two or three superconducting layers formed on a superconducting ground layer and one resistance layer (Non-Patent Document 5: IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1363-1371, 1989; Non-Patent Document 6: IEEE Trans. Applied Superconductivity, vol. 5, no. 2, pp. 2447-2452, 1995).
FIG. 37 is a schematic sectional view of a conventional device structure of this type. This device structure comprises an Nb superconducting ground layer (M1) formed on an oxidized silicon substrate, two Nb superconducting wiring layers (M2 and M3), an Mo resistor layer (RES1), an Nb/AlOX/Nb Josephson junction portion (JJ), and an SiO2 interlayer insulating layer. The lower Nb layer (M2) under the Nb/AlOX/Nb Josephson junction portion is used as a wiring layer.
A device structure of a superconducting RAM is characterized by its memory cell structure. Various memory cell circuits have hitherto been proposed, but basically, it comprises a superconducting loop adapted to store a single flux quantum and a Josephson junction or a gate formed by a Josephson junction which is used for introducing/removing a flux quantum into/from the superconducting loop, and further comprises at least one control wire for controlling introduction/removal of a flux quantum through the Josephson junction. Normally, this control wire is disposed so as to be magnetically coupled to the superconducting loop or the gate formed by the Josephson junction.
According to the foregoing conventional device structure, it is possible to configure a superconducting loop including a Josephson junction, serving as a basic device of a memory cell, and a control wire disposed so as to be magnetically coupled to the superconducting loop. Actually, using this device structure, there has been developed a 4 kbit superconducting RAM (see the foregoing Non-Patent Document 6).
On the other hand, following the increase in RAM capacity, in the normal structure, the number of elements in each of a decoder circuit, a drive circuit, and a sense circuit only increases in proportion to the square root of the capacity of memory cells.
However, the conventional superconducting RAM is divided into the small blocks each having the complete RAM structure including the decoder circuit, the drive circuit, the sense circuit, and the memory cell array. Since the number of blocks increases in direct proportion to the increase in RAM capacity, the numbers of decoder circuits, drive circuits, and sense circuits also increase in direct proportion thereto. Therefore, there has been a problem that the layout area and the power consumption increase in direct proportion to the increase in memory capacity.
Further, in the conventional superconducting RAM, there has been a large problem that since the drive circuit and the sense circuit are formed by the voltage logic type latching devices adapted to operate with the AC power supply, the high-frequency AC power supply is required and hence the power consumption further increases.
In addition, there has been a problem that the conventional superconducting drive circuit requires rectangular-wave signals (level signals) as a data signal and a reset signal and does not operate with single flux quantum (SFQ) pulses. In the conventional sense-bus superconducting sense circuit operable with the DC power supply, it is necessary to detect the fall of a signal in the sense line and, further, it is necessary to adjust switching of the current to the output gate at the proper timing with the clock signal. Therefore, there has been a problem that since the operation margin of the circuit is narrow and further it is necessary to set the sufficient timing margin, it is difficult to operate the circuit at high speed.
Further, following the increase in capacity of the superconducting RAM, it is necessary to carry out signal propagation among many memory cell arrays at high speed. However, in the conventional device structure, since the number of superconducting wiring layers is three or less, a special wiring layer cannot be provided for this signal propagation and hence the speed-up of signal propagation is impeded. Further, when seeking the speed-up of signal propagation with such limited layers, the number of wires arranged two-dimensionally increases and, in this case, the integration scale of the device is lowered.
Further, since one superconducting wiring layer is used for two purposes, i.e. power supply and signal propagation, there has also been a problem that the influence of a magnetic field due to the power supply current tends to occur and hence the operation margin of the circuit is reduced. In addition, there has also been a problem that when the inductance is formed in the power supply line, the layout area increases.
Further, since, in general, the Nb/AlOX/Nb junction is subjected to deterioration in characteristic at a temperature of 200° C. or more, a higher-temperature process cannot be employed in device fabrication. For example, the SiO2 interlayer insulating layer should be formed by sputtering being a low-temperature process when it is formed after forming the Josephson junction. In this case, there are instances where covering of a stepped portion by the SiO2 film is not sufficient so that excellent insulating properties cannot be obtained.